The present invention relates to the field of current injection circuits. More specifically, the present invention relates to the field of differential charge pump circuits.
High speed digital systems, such as engineering workstations and personal computers, require clock sources that have low jitter and low phase lock loop (PLL) bandwidths. Phase jitter in a system clock reduces the effective clock speed of the workstation or personal computer. More processing performance is gained, for a given clock rate, if the clock signal has less jitter. The PLL circuitry typically contains a voltage controlled oscillator (VCO) that receives a voltage level maintained by filter components. Normally, charging currents and voltage controlled oscillator gains are so high that large externally situated filter components are utilized in order to achieve the low jitter and low bandwidth requirements.
In operation, a PLL circuit injects current into filter components to establish a voltage at the input of a voltage controlled oscillator circuit in order to alter the frequency of oscillation of the PLL. This current is then ideally held constant over a long period of time (e.g., a xe2x80x9chold timexe2x80x9d) to maintain the oscillation frequency. During the hold time, the filter elements are electrically sampled by buffer circuits.
There are several disadvantages associated with utilizing large externally situated filter components. One of the disadvantages is that large external, e.g., xe2x80x9coff-chip,xe2x80x9d filter components (e.g., capacitors, etc.) increase the overall cost of the digital system in part by making manufacturing more complex. Another disadvantage is that external components increase the physical size of the digital system. A further disadvantage is that off-chip filter components decrease system reliability by increasing the phase jitter by allowing external noise to be injected into the clock circuit through the PLL filter.
One prior art solution for alleviating the above mentioned disadvantages is to eliminate the external elements of the PLL filter. In order to eliminate external elements, it is necessary to use smaller sized filter components. However, as the size of the filter components are reduced, the amount of current supplied to them typically decreases proportionally in order for the PLL filter to achieve the same bandwidth. In other words, smaller sized filter components typically need to be supplied accurate currents having very small magnitudes to produce the same operational voltage range. Normally, currents are directly generated by utilizing a voltage change across a resistor. But there are disadvantages associated with this prior art technique.
One of the main disadvantages is that it typically requires the use of excessively large resistor values in order to directly generate small magnitude currents from available on-chip circuitry voltages. For example, a 100 nanoamperes (nA) current is directly generated when a 1 volt signal is applied across 10 megaohms (Mxcexa9) of resistance. As such, the fabrication of excessively large resistor values (e.g., 10 Mxcexa9) on-chip typically becomes impractical because they occupy too large of an amount of die area. Therefore, they are not cost effective.
Accordingly, it would be advantageous to provide a system that produces accurate small magnitude currents for particular on-chip circuitry without utilizing a large resistor value. Furthermore, it would be advantageous to provide a system that produces accurate small magnitude currents for particular on-chip circuitry utilizing available on-chip circuitry voltages. The present invention provides these advantages. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
The present invention includes a system that is able to provide a charge pump current having a very small magnitude. The present invention operates in one embodiment as part of an integrated circuit of a semiconductor chip by providing very small magnitude currents to other on-chip circuitry. Specifically, one embodiment of the present invention utilizes an R-2R resistor ladder circuit having moderate sized resistors to progressively reduce a large magnitude current into a very small magnitude current of accurate size. In this manner, available on-chip circuitry voltage can be used to produce the desired small magnitude of current without utilizing excessively large resistors, which can occupy too much die area. This is advantageous when dealing with specific types of on-chip components and circuitry which require accurate currents having very small magnitudes. For example, it may be desirable to integrate filter components (e.g., capacitors) on-chip together with accompanying phase lock loop (PLL) circuitry. However, smaller sized filter components typically need to be supplied accurate charge pump currents having very small magnitudes in order to produce the desired operational bandwidth. As such, the present invention is able to provide accurate charge pump currents having very small magnitudes for the smaller sized filter components from the available on-chip circuitry voltages. Moreover, a system in accordance with the present invention provides these advantages while being fabricated utilizing bipolar technology which is less expensive than BiCMOS technology. The present invention finds particular application within a clock generator circuit where it reduces clock jitter by enabling PLL filter components to be completely integrated on-chip.
More specifically, in a clock generator circuit having a phase lock loop circuit, a subunit circuit comprising: a circuit for providing a stable first current; a semiconductor integrated circuit filter element for providing a voltage to a voltage controlled oscillator circuit, wherein the semiconductor integrated circuit filter element is coupled to receive the stable first current from the circuit; a resistor ladder circuit having n stages, wherein the nth stage is coupled to the semiconductor integrated circuit filter element to inject differential current across the semiconductor integrated circuit filter element; and a buffer circuit for determining a second current signal supplied to a first stage of the resistor ladder circuit.
Embodiments include the above and wherein the circuit for providing a stable first current further comprises: a current source circuit; and a current sink circuit. Additionally, the resistor ladder circuit mentioned above progressively attenuates the second current signal received by the first stage into the differential current. Moreover, the differential current mentioned within the previous paragraph is less than 100 nanoamperes. Furthermore, the resistor ladder circuit mentioned within the previous paragraph is an R-2R resistor ladder circuit. Additionally, the buffer circuit mentioned above is an emitter-coupled logic (ECL) buffer circuit.